As an X-Y address type solid state imaging device, for example, an MOS type solid state imaging device, one configured by unit pixels comprised of three transistors and having a large number of these unit pixels arrayed in a matrix is known.
The configuration of the unit pixel in this case is shown in FIG. 1. As apparent from the figure, a unit pixel 100 has a photodiode (PD) 101, a transfer transistor 102, an amplifier transistor 103, and a reset transistor 104.
In the MOS type solid state imaging device employing the above pixel configuration, during the period in which the row is not selected, the potential of a floating node N101 is reduced to a low level (hereinafter described as the “L level”) from a drain line 105 through the reset transistor 104. When the row is selected, an operation for raising the potential of the floating node N101 to a high level (hereinafter described as the “H level”) is carried out.
In such an MOS type solid state imaging device, as the reset transistor 104, use is made of a depression type transistor. This is employed so as to make the drain voltage serving as a power supply of the pixel portion and the potential of the floating node N101 match without variation when the reset transistor 104 is on.
Accordingly, the floating node potential when the reset transistor 104 is on matches with the potential level of the drain line. As the potential level of the drain line, specifically, for example as described in Patent Document 1, the H level is a power source potential VDD, and the L level becomes 0.4 to 0.7V (the L level may be 0V as well).
Here, consider the potential of the floating node for a selected row and a nonselected row.
First, consider the operation of a selected row.
After the drain line is set at the H level, the reset transistor and the transfer transistor are sequentially turned off→on→off and a reset phase potential and a data phase potential are output. A difference of these signals is output as a light signal via a correlated double sampling (CDS) circuit.
At the time of acquisition of the data phase potential, when the charge of the photodiode is transferred to the floating node, the floating node potential is lowered.
Next, consider the nonselected row.
Both of the reset transistor and the transfer transistor remain in the off state as they are. Only the drain line repeats values of H level and L level.
Patent Document 1: Japanese Patent Publication No. 2002-51263